HDL and circuit design

[changtimwu]

github.com/parallella/oh/sw

• best practice of 20 years of chip design
• silicon proven building blocks

[changtimwu]

http://ccckmit.wikidot.com/ve:main http://inst.eecs.berkeley.edu/~cs150/fa08/Documents/Always.pdf http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

[changtimwu]

picorv32 interesting comments!

https://news.ycombinator.com/item?id=10259733 The actual verilog code is only 1450 lines. I didn't realize that you could be so productive (I've never done any chip design before, but have watched longingly for some time).

The actual verilog is often the easy part. Writing a good simulation (see testbench.v and the firmware folder) to make sure that verilog does what you expect takes a fair amount of work. Getting the verilog to synthesize and meet timing is also another large piece of the work. It appears that (unlike a lot of FPGA projects) the author of this has actually written scripts to automate that part, but you can bet there was a fair amount of trial and error to get those scripts correct. There's always a lot of "fighting the tools" involved in this process.

Besides, it contains formal verification.

http://www.clifford.at/papers/2016/yosys-smtbmc/

[changtimwu]

• http://people.bu.edu/joshi/files/pact2015-eldridge.pdf -- NN accelerator
• http://yuba.stanford.edu/~grg/docs/sdn-chip-sigcomm-2013.pdf -- network processor. SDN chip. P4
• http://users.ece.utexas.edu/~tiwari/pubs/ASPLOS-15-ghostrider.pdf

[changtimwu]

good vliw overview http://twins.ee.nctu.edu.tw/courses/ca_08/literature/11_vliw.pdf