Closed jasonyu1996 closed 6 years ago
The interrupt control system has been integrated into the CPU, and the overall system has passed the Fibonacci test and another test that includes an INT instruction and an ERET instruction.
Next step: design some more sophisticated test cases.
New instructions for interrupt handling created. Some bugs fixed. The system tested on sophisticated test cases covering INT, ERET, MFEPC, MTEPC and MFCS.
Finished. Further tests concerning ISR manipulations will be carried out when the PS/2 controller is added.
It seems that we now have an implementation of interrupt controller.
Next step: passing interrupt signals along the pipeline stages.