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chasep255 / Nexys-4-DDR-Ethernet-Mac

Ethernet MAC for the Digilent Nexys 4 DDR FPGA.
GNU General Public License v3.0
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LAN8270A "Strap" pins should not be driven as inout - they should only be inputs. #2

Open cube1us opened 3 months ago

cube1us commented 3 months ago

The reason you had trouble dynamically configuring the PHY using the strap pins is that the chip is not designed to do that. The strap pins are designed to only be set via pull up or pull down resistors - and the Nexys4 has them pulled up except for NINT/REFCLK0 which has an internal pull up. So all of those inouts should really just be inputs.

From the SMSC LAN8720A data sheet. revision 1.4, page 70:

"Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7, "Configuration Straps," on page 31 for details. Configuration straps must only be pulled high or low and must not be driven as inputs."

BTW, thanks a bunch for this. While I will end up using a different IP stack for my Nexys4 (https://github.com/alexforencich/verilog-ethernet), your logic simplified things for me as I explored how to get things working - in particular, how to properly do a reset of the PHY.

[The aforementioned core can be made to work with the Nexys4 by using the discontinued, but still freely available MII to RMII v2.0 core from Xilinx (perhaps requiring downloading a slightly older version of Vivado), and setting up the correct clocking and a proper reset signal for the chip.]

PS: I also changed the SMI clock from a 400ns period to 440ns, as 400ns was specified as the absolute minimum in the data sheet.

JRJ

chasep255 commented 3 months ago

Thanks for letting me know. This was just a fun project for me to mess around with the chip and verilog. I'm not maintaining it anymore, but if you want to create a pull request with a fix feel free to do so.