Add option for auto-alignment (neat vs. compact) for entity/component prints

[chaseruskin]

Add an additional setting under 'general' for having users decide if they want to have the component declarations print with aligned =, =>, :, etc. Currently, the components print out in what will be called "compact" form where there is no alignment among signal names. Setting it to "neat" will align the respective signal tokens.

[chaseruskin]

The printMapping method for each entity has improved and gained additional parameters to the method for better customization. Some parameters include:

• hang_end (bool) determine if the closing ) deserves its own line
• alignment (bool) determine if spaces between HDL tokens should be auto-aligned to length of longest word
• spaces (int) number of spaces between HDL tokens (=> for vhdl or ( ) for verilog)

[chaseruskin]

These settings will need a home in the settings.cfg file. Potentially:

[HDL-styling]
    hang-end = yes
    align = yes
    spaces = 1

[chaseruskin]

Another HDL-styling option:

setting wire/signal names. For example, rather than defaulting to print out signals/wires of same name as port names, users can optionally add a prefix or suffix to the signals/wires being printed. This may help if users want to find/replace signal names as they are instantiated into their code.

Example:

w_* - will add "w_" to every signal