Open edwardcwang opened 5 years ago
I haven't seen this construct, can you send me the full firrtl file. I will need to see how this thing gets lowered to figure out what's going on. Thanks
Here's a very minimalistic example that just attach
es two IOs:
FIRRTL:
circuit AttachTest :
module AttachTest :
input clock : Clock
input reset : UInt<1>
output io : {in : Analog<1>, out : Analog<1>}
attach (io.in, io.out) @[cmd8.sc 6:9]
Chisel:
class AttachTest extends Module {
val io = IO(new Bundle {
val in = Analog(1.W)
val out = Analog(1.W)
})
attach(io.in, io.out)
}
I'll fixit, I'm curious why you put this issue on chick/visualizer instead of freechipsproject/diagrammer. Accident?
@edwardcwang is this the only use case for attach, there is very little documentation, what should it do? Unlike connect it takes a list of expressions, not an lhs and rhs like connect
W.r.t putting the issue here:
1) Github says that chick/visualizer is the upstream and freechipsproject/diagrammer is a fork. If the freechips one is meant to be the authoritative upstream then we should delete that and move this repo there.
2) The issues tab is missing for me in freechipsproject/diagrammer
Attach is used to connect Analog
nets together. It is a multi-way, undirectioned connect.
e.g. the following line is not recognized by the visualizer