Open chili-chips-ba opened 2 weeks ago
See: https://github.com/chili-chips-ba/openCologne/issues/3#issuecomment-2156305837
As a bare minimum, CologneChip should have at least a 6-month Yosys update cadence, i.e. at least two times a year. Proper SystemVerilog support should also come built-in, be it via Synlig plugin, or by using SV2V preprocessing.
See: https://github.com/chili-chips-ba/openCologne/issues/3#issuecomment-2156305837
As a bare minimum, CologneChip should have at least a 6-month Yosys update cadence, i.e. at least two times a year. Proper SystemVerilog support should also come built-in, be it via Synlig plugin, or by using SV2V preprocessing.