The provided simulation Verilog model of CC_PLL isn't a correct representation of the true CC_PLL's behavior. Whatever parameters put in when instantiating CC_PLL get lost and the output clock frequency is just half the input.
This can be especially confusing when running simulation of the examples built in with the tools.
chili-chips-ba
commented
2 weeks ago
The provided simulation Verilog model of CC_PLL isn't a correct representation of the true CC_PLL's behavior. Whatever parameters put in when instantiating CC_PLL get lost and the output clock frequency is just half the input.
This can be especially confusing when running simulation of the examples built in with the tools.