Open TarikHamedovic opened 2 weeks ago
Hi @gtaylormb. This is essentially:
In a follow up to @hzeller recommendation, we are also planning to bring up Verible-based Linter for opl3_fpga RTL.
Please consider using these flows to make the opl3_fpga RTL even better than it already is.
Verilator Simulation Warnings
While running the synthesis for the OPL3 FM Synthesizer, I encountered several warnings related to the RTL code. Although the synthesis completes successfully due to the Makefile being configured to ignore these warnings, it's crucial to address these warnings for cleaner code and synthesis. Other tools like yosys might treat these warnings as errors, potentially causing issues in the future. To run the Makefile go to 2.sim/ folder and run
make
. The following flags are currently set to ignore warnings in the Makefile:By removing the flags one by one you can see for your self the warnings that Verilator has such as:
I won't list all the warnings here due to readabilty but there are 108 WIDTH warnings, 37 UNUSED warnings, and several minor warnings.
Cocotb Simulation Warnings
Running
make
in the 2.sim/cocoTB folder also results in warnings related to the RTL code:And so on... As said I won't list all the listed warnings and errors.