Improper UART synthesis

[tarik-ibrahimovic]

When implementing a simple UART test, sending 2 RTL hard-coded bytes every 1.6 ms on tx, strange results were observed: Some combinations of bytes transmit correctly, some don't. Important notes: rx functionality works fine, tx of one byte works fine. Example of bytes which produce good transmission: Example of bytes which produce incorrect transmission:

After delving deeper into the problem the following has been concluded: RTL simulation goes well, Synthesis netlist simulation fails. RTL simulation has been verified with both Verilator and Icarus Verilog, while post-synthesis simulation has been done only using Icarus Verilog. Post-synthesis simulation fail also produces a uart_state which goes unknown after the reset (not supposed to happen).

Provided is a synthesis log file which has one ABC warning: synth.log

Here you can find a full test folder structure, including the python script for reading from the FPGA UART uart_test_openCologne.zip.

[chili-chips-ba]

... let's also add that this UART design is hardware-proven in multiple applications, using both Gowin and Xilinx silicon, implemented using their respective proprietary tools.

We wonder if this Yosys issue has to do with FSM recoding:

@tarik-ibrahimovic , can you rerun Yosys with auto-FSM recoding disabled? In any case, report this SIM-SYNTH discrepancy to Yosys

[tarik-ibrahimovic]

Disabling FSM recoding yields in a different but still non-functioning result

[chili-chips-ba]

The fact that we are getting different result for a change in Yosys options is a good data point, and indicative in itself.

[chili-chips-ba]

@pu-cc, could you please take a quick look at the test package that Tarik prepared, reproduce this problem, and provide your expert insights. Note the availability of both pre- and post- synthesis simulation.

Tarik is in the meantime trying to instrument this design with your recently announced ILA...

[pu-cc]

From what I see, this issue also affects the synth_xilinx pass, but synth_ecp5 is fine.

I took a closer look and found inconsistencies in the mapping of the two registers tick_1us_reg and uart_buffer_state. In both cases, mapping of the cell type $_DFFE_xxxx_ to CC_DFF led to an incorrect initial value. Commit https://github.com/pu-cc/yosys/commit/2c25eceb758d514792ac176d63697c6c9e8e917b should fix it. Simulation was fine after synthesis. I will definitely have to run some more tests, but can you please check this, too? Thank you.

[tarik-ibrahimovic]

Synthesis is fine now, but PnR isn't. Take a look at the two simulations (post-PnR on top and post-synthesis on bottom). Post-synthesis simulation works well now, it's matching the RTL sim. Run impl_sim in 2.sim to see post PnR and compare. Also provided is the implementation and synthesis log file. impl.log synth2.log