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chili-chips-ba / openCologne

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne
https://nlnet.nl/project/openCologne
BSD 3-Clause "New" or "Revised" License
46 stars 2 forks source link

GateMate simulation quirks and problems #22

Closed chili-chips-ba closed 2 months ago

chili-chips-ba commented 4 months ago

Given this, and this, and more of that in internal discussion, let's continue with simulation issues using this track.

chili-chips-ba commented 4 months ago

@tarik-ibrahimovic, please continue the sim related discussion on this track

such as: "... on other projects even the post-synth sim doesn't work in Icarus, neither in Verilator, again the simulation doesn't advance. Again I stumbled upon a RTL-hardware inconsistencies which I wanted to take a closer look at but now is extremely challenging..."

@aimamovic6 , the same goes for you sim struggles.

tarik-ibrahimovic commented 4 months ago

We had a problem simulating the post-pnr netlist which contained CC_PLL module. @pu-cc has clarified the source of the issue here.

I just need to touch on the "post-pnr sim works in Verilator, doesn't in iverilog" mentioned by @pu-cc and me, for clarification:

This has been verified by removing define USE_PLL in the cpelib.v and running post-pnr sim in iverilog. It is implied that the new CC_PLL model blocks the post-pnr sim, whether it has the PLL in design or not. This is yet to be fixed.

pu-cc commented 4 months ago

When you use the CC_PLL in the design neither Verilator nor iverilog can simulate post-pnr without editing the post-pnr netlist

Exactly, that's why I suggested manually entering the OUT_CLK parameter as a real value. Next P&R update will pass these parameters from the synthesis netlist to the post-implementation netlist.

When there is no CC_PLL in the design iverilog can't simulate because it's still blocked by the cpelib.v model of CC_PLL but Verilator doesn't mind

If no PLL is used, default parameter for OUT_CLK is zero. Please check the updated cpelib.v; we've already updated it in the toolchain downloads.

chili-chips-ba commented 2 months ago

@tarik-ibrahimovic please advise whether all PLL model questions are now resolved. If so, please close this issue.