Mismatch in post-PnR sim and chip operation

[tarik-ibrahimovic]

uart_tx changes with a change in declared IO ports of the module

In this design, when declaring logic tick_02us in the 1.hw/top.sv as an IO port everything functions correctly (tick_02us is not intended to be real IO, but in cases was used as means to debug).

However, if removed as an IO port, and left just as an internal signal, the uart_tx starts misbehaving. Also, the output duplicate of uart_tx,sent, becomes incorrect. This isn't present in post-PnR sim which seems fine. Important note: When tick_02us is mapped to a location like "IO_NB_A0" it still misbehaves, but if mapped to "IO_NB_A2" like in the repo the design works just fine.

Steps to recreate the issue

These instructions are for the Olimex board:

1. First, run the design as is, following the steps presented in the repo folder
2. At this point everything should seem fine, written data should be the same as read data
3. Comment or delete the tick_02us from 1.hw/top.sv and uncomment the declaration left below logic tick_02us
4. Comment or delete the tick_02us port from 1.hw/constraints/constraints.ccf
5. Remove the tick_02us port from 2.sim/tb.sv to run the simulations correctly
6. Verify that RTL sim matches post-PnR sim by running make then make all_impl
7. See that the board isn't running the design correctly by invoking the python 4.testing/pyauto.py script which communicates via Serial
8. Get an oscilloscope and tie it to the IO_NB_A1 pin and notice that sent which is a duplicate of uart_tx is also incorrect and doesn't match post-PnR sim.

[chili-chips-ba]

@pu-cc , is there anything you still need from Tarik to address this problem?