Issue with using sv2v for a simple Blinky example

[TarikHamedovic]

When trying to use sv2v while specifying localparam COUNTER_WIDTH in SystemVerilog for a blink example like this:

module blink (
    input  logic clk,
    input  logic areset_n,
    output logic led
);

  localparam logic COUNTER_WIDTH = 24;
  logic [COUNTER_WIDTH-1:0] counter;

  always_ff @(posedge clk or negedge areset_n) begin
    if (!areset_n) begin
      counter <= '0;
    end else begin
      counter <= counter + 1'b1;
    end
  end

  assign led = counter[COUNTER_WIDTH-1];

endmodule : blink

When I type sv2v blink.sv --write=adjacent in the terminal I get the following output file in Verilog:

module blink (
    clk,
    areset_n,
    led
);
    input wire clk;
    input wire areset_n;
    output wire led;
    localparam [0:0] COUNTER_WIDTH = 24;
    reg [COUNTER_WIDTH - 1:0] counter;
    always @(posedge clk or negedge areset_n)
        if (!areset_n)
            counter <= 1'sb0;
        else
            counter <= counter + 1'b1;
    assign led = counter[COUNTER_WIDTH - 1];
endmodule

The problem seems to be the localparam [0:0] part, when I remove the [0:0] the example works fine.

Any reason as to why this happens?

[TarikHamedovic]

Problem was that I declared the parameter as logic and not integer.

Should delete this issue.