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chili-chips-ba / wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
https://nlnet.nl/project/KlusterLab-Wireguard
BSD 3-Clause "New" or "Revised" License
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Tool version control and distribution: Central server, Docker, or Nix packages?! #8

Open chili-chips-ba opened 1 day ago

chili-chips-ba commented 1 day ago

Wireguard 1GE FPGA is a complex HW/SW co-development project, with a large team and multidisciplinary needs. As such, it draws from a variety of open source tools that are to be brought in, managed and distributed to team members in a controlled fashion. We absolutely want the entire team to be on the same tool versions!

One option is to host the tools on a central server, which the developers would remotely log into and run everything on. The other option is to use the central server only for the distribution of our approved tool package. In that case, there will be differences between the machines that run the tools, as some developers are using native Linux, others WSL, MSYS2, or other Linux emulation frameworks. There will also be differences in the versions of their OS distro.

This discussion track is to solicit advice and help, both on the conceptual level and practical execution.

For starters, here is a glimpse into how Ibex core and BerkleyLab Bedrock projects handled this task.

chili-chips-ba commented 3 hours ago

Here is an initial tally of tools and IP used for the project:

v5.024 - Verilator (also uses as RTL Linter. The latest is v5.030) v3.3.116 - GTKwave 3.13.0 - Python3 v0.13.1 - Surfer v0.0.12 - SV2V v0.0-3843 - Verible (used as RTL Formater) LATEST - CDC Snitch 2024.2 - Vivado 0.4.7 - Yosys 1.1.0 - PeakRDL 2024.11.22-RISC-V GNU Toolchain (Clang is used as C linter and formatter) 0.12.0 - OpenOCD LATEST - PipelineC HLS LATEST - openXC7

VIP (installed automatically, by Sim Makefile)

v1.11.3 - VProc v1.0.0 - Mem Model v1.1.3 - rv32 ISS
TBD - TCP/IP Packet Generator

IP (pulled in manually, as needed)

v0.0.3 - Ibex Demo System LATEST - Ibex v1.5 - Bringup-Bench LATEST - FPGA Design Elements

Other tools, not managed:

LATEST - Wireshark