Clarification on "redundant fuses" expectation ?

[myviewfinder]

Is the text in Caliptra section below describing Caliptra's internal "redundant fuses" beyond the fuse map registers? Are there any expectation on the SoC about implementing and/or programming "redundant fuses" into Caliptra fuse map registers?

Caliptra specification section Device Resilience Table 12: NIST SP 800-193 requirements, row number 4.3.2 contains description below:

Caliptra relies on redundant fuses to store its configuration data, which is owned and passed to Caliptra through the Mailbox.

[varuns-nvidia]

No, the expectation is entirely on the SoC. Caliptra IP does not implement fuses. See the following text from https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md#fuse-requirements

SoC should ensure that the integrity of each fuse is maintained through the life of the part. The integrity of the fuses can be maintained by fuse redundancy, ECC, or other means determined sufficient by the SoC.

[myviewfinder]

@varuns-nvidia , kindly consider Caliptra specification clarification:

1. Please consider using consistent language in the Caliptra specification section Device Resilience Table 12: NIST SP 800-193 requirements, row number 4.3.2, with the section Fuse Requirements, and

2. Replace the "through the Mailbox" text to "through fuse registers". SoC writes Caliptra fuses via Caliptra fuse registers, not Caliptra Mailbox.

The current sentence in specification section Device Resilience:

"Caliptra relies on redundant fuses to store its configuration data, which is owned and passed to Caliptra through the Mailbox."

An example after combining the bullet list above:

"Caliptra relies on SoC fuse integrity to store its configuration data, which is owned and passed to Caliptra through the fuse registers."

[varuns-nvidia]

Thanks for the suggestion, PR posted.