chipsalliance / Cores-VeeR-EH1

VeeR EH1 core
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Question about pipeline FF enable signals #110

Open tunefish777 opened 2 years ago

tunefish777 commented 2 years ago

Hi,

I'm currently trying to understand the pipeline but I'm puzzled by one small detail. The dec_iX_decode_d signal is used as the highest value of the iX_pipe_en signal which is then shifted down the pipe. From this value, we derive the enable signals (iX_eX_data_en and iX_eX_ctl_en) for the individual pipeline FFs. For the ...data_en signals, this makes sense to me, but the ...ctl_en signals stay active for one additional cycle. This leads to some "random" value being latched in the control FFs one cycle after dec_iX_decode_d changes to 0 (due to stalling etc.). So far, I don't think this "random" value matters, since the piped destination-packet contains a valid-decode flag that is not set for this cycle. But what was the design decision for this behavior? Is this related to the comment that reads "// allow illegals to flow down the pipe"?

I would really appreciate some explanation.

Kind regards