Supporting DCCM without multi-bank Support

[Jagannaths3]

@aprnath , I am trying to use a DCCM without multiple bank access capability. The current DCCM (say DCCM_orig) interface looks like this

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output logic dccm_wren, output logic dccm_rden, output logic [RV_DCCM_BITS-1:0] dccm_wr_addr, output logic [RV_DCCM_BITS-1:0] dccm_rd_addr_lo, output logic [RV_DCCM_BITS-1:0] dccm_rd_addr_hi, output logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data,
input logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, input logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,

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This supports all types of unaligned access. However, I can only have a DCCM, (say DCCM_new) with memory bank structure that has the below interface.

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output logic dccm_wren, output logic dccm_rden, output logic [RV_DCCM_BITS-1:0] dccm_wr_addr, output logic [RV_DCCM_BITS-1:0] dccm_rd_addr, output logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, input logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data,

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DCCM_new originally was 64bits wide, so I can increase the width of dccm_rd_data to 64 from 32 (RV_DCCM_FDATA_WIDTH is 39 - 32 data, 7 ECC). This can support only a small subset of unaligned accesses. Eg : A word (32- bit) access to address 0x0106 (mapped to DCCM_orig), successfully passes as the core splits this into two read accesses, one each to 0x0106 and 0x0109. that get processed simultaneously. However, a word read access to 0x0106 on DCCM_new fails.

Is it possible to configure SweRV to support DCCMs with banking structures that can support data access to only one bank at a time?

Thanks!

[aprnath]

With the current architecture, we need atleast 2 banks to support unaligned read accesses. There is no way to support unaligned access, as designed, with single bank DCCM.