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chipsalliance / Cores-VeeR-EH1

VeeR EH1 core
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Interrupt example #24

Closed Jagannaths3 closed 4 years ago

Jagannaths3 commented 4 years ago

Hi, I am trying to use the interrupt on the SweRV core. I am trying the following 1) Setup interrupt[1] with following features - standard priority order - 0x0 @ mpiccfg gateway configuration set to Edge-triggered, active high - 0x2 @ meigwctrl1 set priority level for interrupt1 to 15 - 0x000F @ meipl1 mask no interrupt - 0x0 @ meipt 0x0 @ meicidpl 0x0 @ meicurpl Enable the interrupt - 0x1 @ meie1 machine interrupt enable - 0x800 @ mie (0x304)

2) put the system to sleep by writing 0x1 to 0x7C6(mpmc)

3) Toggle the interrupt1 bit using testbench.

I see the signal mhwakeup( in dec.tlu) get asserted, but the mhwakeup_ready does not go high since the interrupt is not enabled in the mstatus register.

What is the correct sequence of setting up interrupts and handlers? Can you please provide an example of basic interrupt handler setup and usage? The Example interrupt flows (5.14.1) seems inadequate.

Thanks, Jagannath

olofk commented 4 years ago

Hi,

Perhaps you might be helped by the Zephyr interrupt driver for SweRV here, currently under review for inclusion in Zephyr