Question: how to disable (bypass) data checks in cache?

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

Apache License 2.0

808 stars 219 forks source link

Question: how to disable (bypass) data checks in cache? #37

Closed vit82 closed 4 years ago

vit82 commented 4 years ago

I see that CPU often checks for instruction data in icache even when it's disabled by SWERV configuration (icache_enable=0). This affects overall CPU memory access performance. Please, suggest if it's possible to bypass icache.

aprnath commented 4 years ago

The core is designed to have ICACHE , ICCM or both. It is not optimized for the case that Icache and ICCM are both not enabled. It will function but not efficiently. In other words , cycles are not taken out when Icache is not enabled.

agrobman commented 4 years ago

check for RV_ICACHE_ENABLE define in common_defines.vh if this defined the IC logic will present in design. if you want CPU without IC, you need to use -unset icache_enable switch with swerv.config (-set icache_enable=0, has no effect) ...