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chipsalliance / Cores-VeeR-EH1

VeeR EH1 core
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Problems when using SweRV_fpga with V1.5 of SweRV #44

Closed danidep02 closed 4 years ago

danidep02 commented 4 years ago

Hi, I was using SweRV_fpga (https://github.com/chipsalliance/Cores-SweRV_fpga) with version 1.4 of SweRV with no problems. Everything was working fine.

When I've changed the core to SweRV 1.5, OpenOCD is failing. This is the message that I obtain when running OpenOCD: Open On-Chip Debugger 0.10.0+dev-00530-gaf3a034b5 (2020-02-07-14:17) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html adapter speed: 1500 kHz Info : clock speed 1500 kHz Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (), part: 0x0000, ver: 0x0) Error: Debug Module did not become active. dmcontrol=0x0 Info : Listening on port 3333 for gdb connections Error: Target not examined yet

Do you know which can be the reason?

Thanks, Dani

aprnath commented 4 years ago

Hi, Please note that release 1.5 had an addition port added (dbg_rst_l) which is a system wide reset for the debug module, independent from the core reset. At the very least this should be connected to the core reset signal. If left unconnected, the debug module's behavior would be unpredictable.

Please check this and let us know if you still have issues.

danidep02 commented 4 years ago

Hi, I've connected the new port to the core reset and it works :) Thanks!

aprnath commented 4 years ago

Cool. Thanks for confirming.