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chipsalliance / Cores-VeeR-EH1

VeeR EH1 core
Apache License 2.0
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D-cache to complement I-cache #47

Closed cahz closed 4 years ago

cahz commented 4 years ago

To get the full performance of SweRV, I am aware that you should use the tightly coupled memories (ICCM and DCCM). When using larger external memory, the common way is to attach them via AXI. Then you can use the I-cache for faster access to instructions. However, this option is not available for data accesses. One workaround is to use a DMA engine to transfer data into the DCCM. A more convenient solution would be a D-cache, similar to the existing I-cache. Are there any plans to include such a feature in upcoming releases of SweRV?

agrobman commented 4 years ago

So far there are no plans to add DCache to Swerv EH1. This is pretty substantial design effort and our main customer does not need DCache.