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chipsalliance / Cores-VeeR-EH1

VeeR EH1 core
Apache License 2.0
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Difference behavior for system Bus Access in dbg.sv and RISC-V External Debug Support Version 0.13.2 #5

Closed ycyang0508 closed 5 years ago

ycyang0508 commented 5 years ago

In section 3.12.23 of "RISC-V External Debug Support Version 0.13.2", write "sbdata0" operation will trigger the system bus write access operation. But in dbg.sv, the write or read access operation is decided by sbcs_reg[15] or sbcs_reg[20] and this seems don't match with the specification.

ZvonimirBandic commented 5 years ago

Thanks for moving from Western Digital GitHub. The issue has been assigned, we will respond by early next week.

tmw-wdc commented 5 years ago

Hi Ya-Chau,

Thank you very much for bringing this issue to our attention. We can confirm that this is a bug in our design and will be fixed soon.

Kind regards, Thomas

ycyang0508 commented 5 years ago

glad to learn something new from SweRV and can contribute something to it at the same time.

jrahmeh commented 5 years ago

Fixed in version 1.2.