tmw-wdc
commented
4 years ago Hi,
Please have a look at Section 3.4 of the ratified RISC-V Privileged spec. NMIs can destroy processor state and it can therefore not be expected that normal program execution can resume, especially in the case of NMI storms.
We have added the following note to Section 2.15 of the SweRV EH1 PRM v1.8 release to emphasize this:
Note: NMIs are typically fatal! Section 3.4 of the RISC-V Privileged specification [2] states that NMIs are only used for hardware error conditions and cause an immediate jump to the address at the NMI vector running in M-mode regardless of the state of a hart’s interrupt enable bits. The NMI can thus overwrite state in an active M-mode interrupt handler and normal program execution cannot resume. Unlike resets, NMIs do not reset hart state, enabling diagnosis, reporting, and possible containment of the hardware error. Because NMIs are not maskable, the NMI handling routine performing diagnosis and reporting is itself susceptible to further NMIs, possibly making any such activity meaningless and erroneous in the face of error storms.
Hi SIR: If the A instruction triggers the NMI, the B instruction that follows is related to the A instruction, and the nmi interrupt processing function cannot continue to execute through the mepc return. If the following B instruction and A instruction are not related, the nmi interrupt processing function can return to normal execution through mepc.