Closed crazy-catlady closed 3 years ago
this core should be able to execute 2 integer instructions per clock. Make sure you are running code from the cache and fast external memory or from ICCM. the MRAC CSR register needs to be programmed to enable caching ...
I turned on the icache and now it works as expected after the respective instructions are cached. Thanks!
However, I do not need 16 kB of icache, i want to have way less.
Is it safe to change NUM_WAYS
and NUM_BANKS
(https://github.com/chipsalliance/Cores-SweRV/blob/7332edc0adaa7e9a0c842d169154429e8d987786/design/ifu/ifu_ic_mem.sv#L228:L229) to do so?
you can set cache size to 8K, I think - run swerv.config -help for possible build parameters ranges. BTW, you can check out more modern smaller EL2 core ...
Ok, I managed to tweak it down to 2048 Byte. However, it is more of a hack...I had to add modules to mem_lib.sv and modify the config script of course.
The EL2 does not exactly fit my purposes, since I need a core as pipelined as possible, preferably dual issue.
However, thank you very much for your help. I really appreciate it. All my questions are resolved now.
I have the following program:
The execution trace like this:
What I notice here is that it takes 10 cycles for the new instructions (5,6) to arrive at the decoder. This is not beneficial for fast execution, since the CPU is kind of idle for 5 cycles between writing instructions 3 and 4 and reading instructions 5 and 6.
Are there configuration parameters to increase the instruction/fetch buffer? Such that it is possible to have more than 4 instructions in execution? I also couldn't really find out if this is due to the instruction buffer size in the decoder (which seems to have 4 instruction slots but somehow only has 2) or the fetch buffer size in the IFU.
Any ideas?