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chipsalliance / Cores-VeeR-EH1

VeeR EH1 core
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SweRV build breaks on latest Verilator #9

Closed toddstrader closed 5 years ago

toddstrader commented 5 years ago

Just a heads-up. I'm working on head-to-head Verilator CI with external projects and found that the latest Verilator tosses some width warnings on the SweRV build: https://www.veripool.org/issues/1483-Verilator-Make-verilator_ext_tests-head-to-head

I'm sure this isn't urgent, so I can touch things up but I won't be able to get to it for a week or so. I thought I'd post here in case someone cares before then.

ZvonimirBandic commented 5 years ago

Todd, we will look into this as well. When/if we eliminate SweRV being issue, we will let you know here.

aprnath commented 5 years ago

These are warnings in the genvar procedures. 

   for (genvar i=1; i<40; i++) begin
      assign error_mask[i-1] = (ecc_check[5:0] == i);
   end

I am not sure these should be flagged or cause build failure.

toddstrader commented 5 years ago

Yeah, sorry I should have circled back here. This is being tracked on Verilator now with the intention of reverting to the old behavior. SweRV shouldn't need to change.

https://www.veripool.org/issues/1487-Verilator-New-WIDTH-warnings-on-genvars