build error with target=high_perf

[kidonglee]

I got error messages as below when running simulation with target=high_perf. default target has no problem but high_perf target has the problem. Please help me.

[config & simualtion] configs/swerv.config -target=high_perf make -f tools/Makefile verilator target=high_perf

[simulation log] BUILD_PATH=snapshots/high_perf /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/configs/swerv.config -target=high_perf

SweRV configuration for target=high_perf

swerv: no_secondary_alu = 0 swerv: load_to_use_bus_plus1 = 1 swerv: lsu_stbuf_depth = 10 swerv: dma_buf_depth = 5 swerv: verilator = swerv: load_to_use_plus1 = 0 swerv: opensource = 0 swerv: lsu_num_nbload = 8 swerv: fast_interrupt_redirect = 1 swerv: fpga_optimize = 0 swerv: timer_legal_en = 1 swerv: num_threads = 2 swerv: dccm_num_banks = 8 swerv: dccm_enable = 1 swerv: dccm_region = 0xf swerv: dccm_offset = 0x40000 swerv: dccm_size = 128 swerv: bht_addr_lo = 3 swerv: bht_size = 4096 swerv: inst_access_addr5 = 0x00000000 swerv: data_access_mask6 = 0xffffffff swerv: data_access_enable7 = 0x0 swerv: data_access_addr1 = 0x00000000 swerv: inst_access_enable4 = 0x0 swerv: data_access_mask3 = 0xffffffff swerv: inst_access_mask3 = 0xffffffff swerv: data_access_mask4 = 0xffffffff swerv: data_access_mask0 = 0xffffffff swerv: data_access_enable3 = 0x0 swerv: inst_access_enable3 = 0x0 swerv: inst_access_mask7 = 0xffffffff swerv: inst_access_addr4 = 0x00000000 swerv: inst_access_addr1 = 0x00000000 swerv: inst_access_mask5 = 0xffffffff swerv: inst_access_mask2 = 0xffffffff swerv: data_access_enable2 = 0x0 swerv: data_access_addr7 = 0x00000000 swerv: data_access_addr3 = 0x00000000 swerv: data_access_enable0 = 0x0 swerv: inst_access_enable1 = 0x0 swerv: data_access_enable4 = 0x0 swerv: inst_access_enable6 = 0x0 swerv: data_access_enable1 = 0x0 swerv: inst_access_mask1 = 0xffffffff swerv: inst_access_addr6 = 0x00000000 swerv: data_access_mask2 = 0xffffffff swerv: data_access_addr6 = 0x00000000 swerv: inst_access_enable7 = 0x0 swerv: inst_access_addr7 = 0x00000000 swerv: data_access_addr2 = 0x00000000 swerv: data_access_addr0 = 0x00000000 swerv: inst_access_enable0 = 0x0 swerv: data_access_addr5 = 0x00000000 swerv: data_access_mask7 = 0xffffffff swerv: inst_access_addr3 = 0x00000000 swerv: data_access_mask5 = 0xffffffff swerv: inst_access_enable5 = 0x0 swerv: data_access_addr4 = 0x00000000 swerv: inst_access_mask0 = 0xffffffff swerv: data_access_enable6 = 0x0 swerv: data_access_mask1 = 0xffffffff swerv: inst_access_addr0 = 0x00000000 swerv: inst_access_addr2 = 0x00000000 swerv: data_access_enable5 = 0x0 swerv: inst_access_mask6 = 0xffffffff swerv: inst_access_mask4 = 0xffffffff swerv: inst_access_enable2 = 0x0 swerv: ifu_bus_id = 1 swerv: dma_bus_prty = 2 swerv: sb_bus_tag = 1 swerv: dma_bus_id = 1 swerv: lsu_bus_tag = 4 swerv: bus_prty_default = 3 swerv: ifu_bus_tag = 4 swerv: ifu_bus_prty = 2 swerv: lsu_bus_prty = 2 swerv: sb_bus_prty = 2 swerv: sb_bus_id = 1 swerv: lsu_bus_id = 1 swerv: dma_bus_tag = 1 swerv: btb_index1_lo = 3 swerv: btb_addr_lo = 3 swerv: btb_size = 512 swerv: pic_region = 0xf swerv: pic_meigwctrl_offset = 0x4000 swerv: pic_meip_count = 4 swerv: pic_mpiccfg_offset = 0x3000 swerv: pic_meipt_count = 127 swerv: pic_meip_mask = 0x0 swerv: pic_meipl_offset = 0x0000 swerv: pic_meitp_offset = 0x1800 swerv: pic_meigwclr_offset = 0x5000 swerv: pic_meidels_count = 127 swerv: pic_size = 32 swerv: pic_meie_count = 127 swerv: pic_meidels_offset = 0x6000 swerv: pic_meipl_count = 127 swerv: pic_total_int = 127 swerv: pic_meitp_mask = 0x0 swerv: pic_offset = 0xc0000 swerv: pic_mpiccfg_mask = 0x1 swerv: pic_meitp_count = 127 swerv: pic_meigwctrl_mask = 0x3 swerv: pic_2cycle = 1 swerv: pic_meipt_offset = 0x3004 swerv: pic_meipt_mask = 0x0 swerv: pic_meidels_mask = 0x1 swerv: pic_meie_offset = 0x2000 swerv: pic_meip_offset = 0x1000 swerv: pic_meigwctrl_count = 127 swerv: pic_meigwclr_count = 127 swerv: pic_meigwclr_mask = 0x0 swerv: pic_meipl_mask = 0xf swerv: pic_mpiccfg_count = 1 swerv: pic_meie_mask = 0x1 swerv: ret_stack_size = 4 swerv: icache_banks_way = 2 swerv: icache_size = 32 swerv: icache_bank_width = 8 swerv: icache_2banks = 1 swerv: icache_ln_sz = 64 swerv: icache_ecc = 1 swerv: icache_waypack = 0 swerv: icache_enable = 1 swerv: icache_num_ways = 4 swerv: iccm_enable = 1 swerv: iccm_region = 0xe swerv: iccm_offset = 0xe000000 swerv: iccm_size = 64 swerv: iccm_num_banks = 4 swerv: Writing snapshots/high_perf/eh2_pdef.vh swerv: Writing snapshots/high_perf/eh2_param.vh swerv: Writing snapshots/high_perf/common_defines.vh swerv: Writing snapshots/high_perf/defines.h swerv: Writing snapshots/high_perf/pd_defines.vh swerv: Writing snapshots/high_perf/whisper.json swerv: Writing snapshots/high_perf/perl_configs.pl riscv64-unknown-elf-cpp -Isnapshots/high_perf /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench/asm/hello_world.s > hello_world.cpp.s riscv64-unknown-elf-as -march=rv32gc hello_world.cpp.s -o hello_world.o Building hello_world riscv64-unknown-elf-ld -m elf32lriscv --discard-none -T/home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench/link.ld -o hello_world.exe hello_world.o riscv64-unknown-elf-objcopy -O verilog --only-section ".data" --change-section-lma .data-0x10000 hello_world.exe data.hex riscv64-unknown-elf-objcopy -O verilog --only-section ".text*" hello_world.exe program.hex riscv64-unknown-elf-objdump -S hello_world.exe > hello_world.dis riscv64-unknown-elf-nm -f posix -C hello_world.exe > hello_world.tbl Completed building hello_world echo '`undef ASSERT_ON' >> snapshots/high_perf/common_defines.vh verilator '-UASSERT_ON' --cc -CFLAGS "-std=c++11" snapshots/high_perf/common_defines.vh /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/design/include/eh2_def.sv snapshots/high_perf/eh2_pdef.vh \ -Isnapshots/high_perf -I/home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench -f /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench/flist \ -Wno-WIDTH -Wno-UNOPTFLAT /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench/tb_top.sv /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench/ahb_sif.sv --top-module tb_top \ -exe test_tb_top.cpp --autoflush cp /home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/testbench/test_tb_top.cpp obj_dir/ make -C obj_dir/ -f Vtb_top.mk OPT_FAST="-O2" make[1]: directory '/home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/obj_dir' enter g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++11 -O2 -c -o test_tb_top.o test_tb_top.cpp /usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_top.cpp Vtb_top_024unit.cpp Vtb_top_eh2_ifu_aln_ctlpi15.cpp Vtb_top_eh2_dec_gpr_ctlpi18.cpp Vtb_top_eh2_ifu_mem_ctl_thrpi38.cpp Vtb_top_eh2_dec_campi39.cpp Vtb_top_eh2_dec_tlu_ctl__pi40.cpp Vtb_top_eh2_lsu_bus_bufferpi42.cpp > Vtb_topALLfast.cpp g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++11 -O2 -c -o Vtb_topALLfast.o Vtb_topALLfast.cpp g++: internal compiler error: killed (program cc1plus) Please submit a full bug report, with preprocessed source if appropriate. See file:///usr/share/doc/gcc-7/README.Bugs for instructions. /usr/local/share/verilator/include/verilated.mk:206: recipe for target 'Vtb_top__ALLfast.o' failed make[1]: *** [Vtb_topALLfast.o] Error 4 make[1]: directory '/home/kdlee/work/riscv/chipsalliance/swerv_eh2/Cores-SweRV-EH2/obj_dir' exit tools/Makefile:86: recipe for target 'verilator-build' failed make: *** [verilator-build] Error 2

[agrobman]

try to run with Cadence or VCS ...

[wsnyder]

It's perhaps running out of memory, check your "ulimit" setting, and also watch "top".

Also it looks like you might be using an older Verilator, try a newer one as it will split up the files for GCC and might avoid this GCC problem.

[kidonglee]

try to run with Cadence or VCS ...

Thanks. But those commercial simulators are not available now for me.

[kidonglee]

It's perhaps running out of memory, check your "ulimit" setting, and also watch "top".

Also it looks like you might be using an older Verilator, try a newer one as it will split up the files for GCC and might avoid this GCC problem.

Thanks for the suggestion. I will try it and let you know the results, soon.

[agrobman]

@wsnyder - what version should we use? is there a switch to force the "split" verilator output? I see the failure with 4.030 ..

[wsnyder]

You can use "--output-split 20000", but would recommend using 4.102.

[agrobman]

Hi @wsnyder , could you, please, check our build command with the latest verilator? I'm getting:

verilator '-URV_ASSERT_ON' --cc -CFLAGS "-std=c++11" snapshots/default/common_defines.vh design/include/ehx2_def.sv snapshots/default/ehx2_pdef.vh \ -Isnapshots/default -I/testbench -f testbench/flist \ -Wno-WIDTH -Wno-UNOPTFLAT testbench/tb_top.sv testbench/ahb_sif.sv --top-module tb_top \ -exe test_tb_top.cpp --autoflush cp testbench/test_tb_top.cpp obj_dir/ make -C obj_dir/ -f Vtb_top.mk OPT_FAST="-O2" make[1]: Entering directory obj_dir' Vtb_top.mk:57: ....veripool/verilator/4.102/include/verilated.mk: No such file or directory make[1]: *** No rule to make target..veripool/verilator/4.102/include/verilated.mk'. Stop. make[1]: Leaving directory `obj_dir' make: *** [snapshots/default/defines.h] Error 2

[wsnyder]

....veripool/

I suspect you have VERILATOR_ROOT misset in your environment.

Note that SweRV + verilator is tested nightly as part of https://github.com/verilator/verilator_ext_tests so is good (except for I broke it for unrelated reasons a few minutes ago ;)

[agrobman]

are you running our makefile?

[agrobman]

BTW, any idea why EH2 compiles slower than EH1 ?

[wsnyder]

Yes, assuming you mean tools/Makefile.

I haven't compared compile times between the projects, so I don't know, but as a guess does RV_FPGA_OPTIMIZE default the same?

[agrobman]

there was the gap before FPGA_OPTIMIZE I guess this might be due high usage of parameter structure in 2nd gen cores vs defines in EH1. VCS/XRUN compile times almost the same for both designs ...

[agrobman]

@wsnyder - with new verilator the compilation is terribly slow ( high performance target) even single threaded version takes more than 30 min (I killed it)

I guess you don't use module - subroutine concept: everything is flattened...

[kidonglee]

You can use "--output-split 20000", but would recommend using 4.102.

After adding the option "--output-split 20000" to verilator, simulation works well. My error is resolved, now. Thank you very much.