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chipsalliance / Cores-VeeR-EH2

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number of instr buffer mentioned in PRM #26

Closed vignajeth closed 3 years ago

vignajeth commented 3 years ago

Hi, i notice that the PRM says in section 1.3.1 "In the ‘Decode’ stage, up to 2 instructions from 4 instruction buffers are decoded.". But i don't think the Decode stage has 4 instruction buffers based on the below lines in RTL. https://github.com/chipsalliance/Cores-SweRV-EH2/blob/a95fdb81ea6dc19239cfe2953ef00710a6f1cf2a/design/dec/eh2_dec.sv#L688-L693

Let me know if i am wrong

vignajeth commented 3 years ago

i misunderstood each buffer can push out two instruction