Improved riscv-dv CI tests - Githubissues

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html

Apache License 2.0

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Improved riscv-dv CI tests #117

Closed mkurc-ant closed 9 months ago

mkurc-ant commented 10 months ago

This PR enhances riscv-dv CI tests by separating code generation and test execution stages. The PR enables the following tests:

riscv_rand_instr_test
riscv_rand_jump_test
riscv_jump_stress_test
riscv_loop_test
riscv_unaligned_load_store_test
riscv_non_compressed_instr_test
riscv_no_fence_test
riscv_illegal_instr_test
riscv_hint_instr_test
riscv_ebreak_test
riscv_ebreak_debug_mode_test
riscv_full_interrupt_test
riscv_mmu_stress_test (though VeeR does not have MMU so the test does not actually use it)
riscv_pmp_test

github-actions[bot] commented 9 months ago

Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions[bot] commented 9 months ago

Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions[bot] commented 9 months ago

Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions[bot] commented 9 months ago

Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions[bot] commented 9 months ago

Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

tmichalak commented 9 months ago

LGTM