Closed koluckirafal closed 12 months ago
Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
I've rebased this branch to remove conflicts after recent main
branch merges. Linter suggestions were addressed through adding waiver rules. Formatter suggestions were addressed partially. More formatting and linting improvements will be introduced in a follow up PR.
Links to coverage and verification reports for this PR (#119) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
LGTM
This PR adds Physical Memory Protection unit, compatible with RISC-V Privileged Architectures Machine-Level ISA specification. A minimal PMP software test is also added, which is used for veryfing if exceptions are properly raised on access violations. PyUVM-based tests are added as well.