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chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core
https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html
Apache License 2.0
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Swerv RISC V #137

Closed navroops17 closed 5 months ago

navroops17 commented 8 months ago

Hi I am trying to synthesize Swerv a RISC V and can anyone help me out how can I do it. Where to do and how to do. Please

mkurc-ant commented 8 months ago

Hi.

The first thing to do is configuring VeeR. Please refer to the README.md (this point https://github.com/chipsalliance/Cores-VeeR-EL2#building-a-model) how to do that.

Following steps depend on the synthesis toolchain you use. The flist file (https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/design/flist) lists all VeeR sources needed for synthesis / simulation. You also need to add include path that points to the generated configuration (by default it generates under snapshots/default).

mgielda commented 5 months ago

Closing, assuming that this is solved.