Closed robertszczepanski closed 9 months ago
Links to coverage and verification reports for this PR (#144) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
Links to coverage and verification reports for this PR (#144) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
Links to coverage and verification reports for this PR (#144) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
LGTM
This PR exposes ICCM and DCCM memory instances outside of the VeeR EL2 core so it would be possible to use external memory cells and connect them to the core ports.
Related to #145.