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chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core
https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html
Apache License 2.0
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SRAM instance export #145

Open calebofearth opened 7 months ago

calebofearth commented 7 months ago

Request that SRAM instances (ICCM, DCCM, ICache) be moved outside of the VeeR core. Connections from internal modules should be exported to allow integrators to connect proprietary SRAM components. This could be done similarly to how Caliptra has implemented it with a SystemVerilog interface.

As part of this feature change, we also request that the SRAM interface be refactored to make the separation between data and ECC more clear. This request tracks https://github.com/chipsalliance/caliptra-rtl/issues/125. Currently, the internal memories have multiple banks, with data and ecc aggregated into a single data bus for each bank, which makes the integrator's job more difficult when implementing system level reliability checks.

algrobman commented 4 months ago

there would be better way to use proprietary SRAMs RTL memories library modules can be replaced with custom onces, instantiating memory vendors verilogs ...

algrobman commented 4 months ago

does this really work? see https://github.com/chipsalliance/Cores-VeeR-EL2/issues/163