As was done in the Caliptra VeeR core instance (here), it is useful to export SRAM ECC status signals so that integrators can make use of the status for RAS features. In some cases, ECC errors may occur that render the VeeR core unable to execute recovery code (such as code that reads internal mcause/mscause registers). Some ECC errors are not reported explicitly (such as an ICCM ECC error during an LSU read), so there is no way to diagnose corrupted bits as the root cause of the issue in lab debug.
As was done in the Caliptra VeeR core instance (here), it is useful to export SRAM ECC status signals so that integrators can make use of the status for RAS features. In some cases, ECC errors may occur that render the VeeR core unable to execute recovery code (such as code that reads internal mcause/mscause registers). Some ECC errors are not reported explicitly (such as an ICCM ECC error during an LSU read), so there is no way to diagnose corrupted bits as the root cause of the issue in lab debug.