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chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core
https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html
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Add JTAG type as a configurable parameter #152

Open robertszczepanski opened 7 months ago

robertszczepanski commented 7 months ago

There is a new VeeR config parameter jtag_type that accepts values cltapc (centralized TAP controller) and emtapc (Embedded TAP controller). The first one supports IDCODE TAP command, the latter does not (responds with 0). By default cltapc is selected which keeps IDCODE command enabled. When emtapc is selected, RV_JTAG_NO_IDCODE define is generated which disabled IDCODE command.

JTAG ID is also set to 0 by default in the testbench.

Solves #146.

github-actions[bot] commented 7 months ago

Links to coverage and verification reports for this PR (#152) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions[bot] commented 7 months ago

Links to coverage and verification reports for this PR (#152) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

algrobman commented 7 months ago

Are you sure this change is compatible with JTAG standard and RISCV debug spec?

tmichalak commented 7 months ago

As far as we understand, according to the JTAG standard (1149.1 section 8.2.1):

a) Public instructions shall be available for use by purchasers of a component.
b) The following public instructions shall be provided in all components claiming conformance to this
standard: BYPASS, SAMPLE, PRELOAD, and EXTEST (see 8.4, 8.6, 8.7, and 8.8, respectively).
c) If the optional device identification register is included in a component, the IDCODE instruction shall be provided

which basically seems to imply that IDCODE is optional.

Now, the riscv-debug spec in chapter 6 (Debug Transport Module) says:

An implementation can be compliant with this specification without implementing any of this section. In that case it must be advertised as conforming to “RISC-V Debug Specification 0.13.2, with custom DTM.” If the JTAG DTM described here is implemented, it must be advertised as conforming to the “RISC-V Debug Specification 0.13.2, with JTAG DTM

This means that removing the IDCODE from DTM of VeeR is compliant with both specifications, however we might need to issue a warning upon the generation of the VeeR configuration without the IDCODE that it is compliant with the "RISC-V Debug Specification, with custom DTM instead of with JTAG DTM.

github-actions[bot] commented 7 months ago

Links to coverage and verification reports for this PR (#152) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/