Add insertion of include guards to VeeR config files, move assert enable flag to Makefile

[koluckirafal]

Fixes #150.

Changes:

• veer.config now adds guards to the generated Verilog include files to prevent multiple inclusion in RTL
• RTL assertions are now enabled by passing assert=1 argument to Makefile while running simulations instead of using configuration flag.

[github-actions[bot]]

Links to coverage and verification reports for this PR (#154) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

[tmichalak]

LGTM