CDC Error

[Syed-mudabbir-ahsan]

Hi

We are facing CDC issue as shown below:

Please check below schematic :

We have added below constraints as mentioned in integration spec but still facing same issue:

Do we need to add a synchronizer in the path, could you please help us to check?

[algrobman]

1) you can't use simple synchronizers to pass a bus to another clocking domain. You'll get bit divergence. 2) there is no need in the synchronizers for buses passing between TCK and CLK clocks domains. TAP controller and Debug Module (DM) logical designs guarantee that flops from both sides sample other side buses when they are stable. Read and Write control signals from TCK clock domain to DM are synchronized to the CPU CLK clock.

Specifically for this path dmi_reg_rdata from CLK clock domain is latched at one TCK clock, but sampled by JTAG SR register in different TCK clock. (TCK clock should be at least 2 times slower than CLK to make this circuit work reliably, which is normally a case - CPU is clocked by 100s MHz clock while TCK is 10MHz or less )