Debug Module reset dbg_rst_l resets the Debug module and synchronizers between the JTAG interface and the core complex,
The core complex reset signal rst_l resets the entire VeeR EL2 core complex.
To achieve above reset scenario rst_l shold be ORed with dbg_rst_l and this ORed reset named as core_rst_l should be reaching all VeeR EL2 core as mentioned in below comment
But in the RTL rst_l is ANDed with dbg_core_rst_l, and since currently we are not using debug module and hence we are not enabling dbg_rst_l or dbg_core_rst_l with external debugger, due to which rst_l reset is not reaching the veer el2 core modules because of AND logic with dbg_core_rst_l.
Can you please let me know if my above understanding is correct, if yes then how can the rst_l reach core modules with dbg_rst_l and dbg_core_rst_l being unused.
Hi Team,
Debug Module reset dbg_rst_l resets the Debug module and synchronizers between the JTAG interface and the core complex, The core complex reset signal rst_l resets the entire VeeR EL2 core complex. To achieve above reset scenario rst_l shold be ORed with dbg_rst_l and this ORed reset named as core_rst_l should be reaching all VeeR EL2 core as mentioned in below comment
But in the RTL rst_l is ANDed with dbg_core_rst_l, and since currently we are not using debug module and hence we are not enabling dbg_rst_l or dbg_core_rst_l with external debugger, due to which rst_l reset is not reaching the veer el2 core modules because of AND logic with dbg_core_rst_l.
Can you please let me know if my above understanding is correct, if yes then how can the rst_l reach core modules with dbg_rst_l and dbg_core_rst_l being unused.
Thanks.