Open wsipak opened 3 days ago
There's a mismatch in port widths because these signals are defined as [6:0] in el2_mem_if.
[6:0]
el2_mem_if
Links to coverage and verification reports for this PR (#204) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/
There's a mismatch in port widths because these signals are defined as
[6:0]
inel2_mem_if
.