Add a way of injecting user module for clock gate(s)

[mkurc-ant]

This PR allows injecting user modules that replace clock gates without the need for modifying RTL code (answer to https://github.com/chipsalliance/Cores-VeeR-EL2/issues/50).

The config script allows to set additional parameters which end up in code as capitalized defines:

• tech_specific_ec_rv_icg - enables usage of the user module
• user_ec_rv_icg - specifies the module name

There's an example user module in testbench/user_cells.sv that can be used to test the new behavior. One can do:

configs/veer.config -set=fpga_optimize=0 -set=user_ec_rv_icg=user_clock_gate -set=tech_specific_ec_rv_icg=1
make -f tools/Makefile

which will run verilated simulation that uses the user module.

[rahuljainNV]

This change looks good to me.