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chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core
https://chipsalliance.github.io/Cores-VeeR-EL2/html/
Apache License 2.0
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[HDL 9-849] #6

Closed altuSemi closed 4 years ago

altuSemi commented 4 years ago

Hi,

Thanks for the repository. I got this error in Vivado 2020.1: [HDL 9-849] Syntax error : file ended before end of clause. ["../Cores-SweRV-EL2/snapshots/default/el2_param.vh":156] Seems like the parameter instance is not parsed correctly.

Also, what is the highest frequency I can expect on FPGA?

Thanks

agrobman commented 4 years ago

do you see compilation problems with other tools verilator/vcs/xrun?

FPGA implementation should run at 50-100MHz ...

olofk commented 4 years ago

I haven't tried with Vivado 2020.1 but it builds fine in vivado 2019.1 when using FuseSoC. If you install FuseSoC, you can then add SweRV EL2 as a library with fusesoc library add el2 https://github.com/chipsalliance/Cores-SweRV-EL2 and run 'fusesoc run --target=synth chipsalliance.org:cores:SweRV_EL2` to have it building for vivado.

olofk commented 4 years ago

hmm.. I just noticed that #3 isn't applied yet, so the FuseSoC builds are currently broken

altuSemi commented 4 years ago

Eventually it was a config issue, closing. Thanks

JavariaK commented 3 years ago

Eventually it was a config issue, closing. Thanks

Can you describe what was the issue and how was it resolved? Thank you