Open upadhyayulakiran opened 1 year ago
@mgielda @kgugala - do either of you know if there is someone that owns/changes verilator code for issues like this?
@upadhyayulakiran can you point me to the code with the smoke_test_clk_gating test you are referring to?
@tmichalak, apologies for the late response. It looks like that test did not get merged yet. Same issue exists with this test: src/integration/test_suites/smoke_test_cg_wdt
The test hangs and PC keeps going in a loop after core wakes up from halt.
When VEER is used in the Caliptra FPGA, we observe the same behavior. I cannot build the default TEC_RV_ICG defined in beh_lib.sv for FPGA and the USER_EC_RV_ICG I can get to work isn't identical logically. I am temporarily working around this by using free_l2clk as the clock signal for flush_lower_ff.
Scenario:
Please use smoke_test_clk_gating to reproduce the issue in Verilator