chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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Question about filtering out nonsythesisable constructs #2662

Closed kamilrakoczy closed 2 years ago

kamilrakoczy commented 2 years ago

I'm trying to filter-out nonsythesisable constructs in yosys. WIP branch can be found here: https://github.com/SymbiFlow/yosys-f4pga-plugins/pull/243

I'm using following test:

module dut();
initial begin
  $displayb("\nTEST PASSED CHECKS");
end
endmodule

According to SynthSubset displayb should be marked as nonsythesisable: https://github.com/chipsalliance/UHDM/blob/master/templates/SynthSubset.cpp#L42, but it is still present in the UHDM:

   \_initial: , parent:work@dut
     |vpiStmt:
     \_begin: (work@dut), line:2:9, endln:4:4
       |vpiFullName:work@dut
       |vpiStmt:
       \_sys_func_call: ($displayb), line:3:3, endln:3:37, parent:work@dut
         |vpiArgument:
         \_constant: , line:3:13, endln:3:35, parent:$displayb
           |vpiDecompile:\nTEST PASSED CHECKS
           |vpiSize:20
           |STRING:\nTEST PASSED CHECKS
           |vpiConstType:6
         |vpiName:$displayb

I've also tried to change 3rd argument of SynthSubset to true, but it also didn't result in error and instead it displays name of the function to stdout (it doesn't happen when 3rd argument is set to false):

 1. Executing UHDM frontend.                                                                                                                                   
$displayb                                                           
design: (work@dut)                                                
 |vpiName:work@dut                        
 |uhdmallPackages:                                         
 \_package: builtin (builtin::), file:, parent:work@dut
 ...

Parsing this test with surelog and -synth option, results in error.

Is this expected behavior? Do I need to parse annotate set myself or nodes from UHDM should be automatically deleted by listen_designs?

Used UHDM version: ad9a41ed8dd74964401586b26843f3aca37fcab5 Used Surelog version: 5d993c5e64ae48192144217dff96806460dca6ac

alaindargelas commented 2 years ago
alaindargelas commented 2 years ago

Please note that UHDM has a client payload datastructure, you can use that to annotate the property on each node.

ClientData BaseClass::Data() const { return clientData_; } void BaseClass::Data(ClientData data) { clientData_ = data; }

kamilrakoczy commented 2 years ago

Ok, thank you. I was able to parse the set in yosys code and filter-out nonsythesisable objects.