chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Apache License 2.0
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Concatenation with an equality test result does not behave as expected #3967

Closed sgherbst closed 1 month ago

sgherbst commented 1 month ago

Noticed that a module doesn't get instantiated in a conditional statement in a generate block when the condition uses a parameter calculated by concatenating with an equality test result. It looks like this also happens if a relational operator is used.

A.v

module A;
    parameter N = {1'b0, (1 == 1)};

    generate
        if (N == 2'b01) begin
            B b();
        end
    endgenerate
endmodule

B.v

module B;
endmodule

Command:

surelog -nocache -parse -nouhdm +libext+.v -y . A.v

Output in slpp_all/file_elab.lst

/path/to/slpp_all/lib/work/A.v

Excepted result: seeing both A.v and B.v in file_elab.lst

Surelog 1.82 macOS 12.6.6

alaindargelas commented 1 month ago

Works like a charm, can't reproduce. Rebuild Surelog from scratch.

sgherbst commented 1 month ago

Thanks! Can confirm that this issue is resolved after building from the latest commit (97e3ae6). If you have a chance, would you mind creating a 1.83 release?

hzeller commented 1 month ago

I take care of creating a new release 1.83 of UHDM and Surelog if you don't mind @alaindargelas ?

alaindargelas commented 1 month ago

Sure @hzeller

hzeller commented 1 month ago

Alright, tagged UHDM and Surelog with 1.83

sgherbst commented 1 month ago

Thank you!