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chipsalliance / UHDM-integration-tests

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Earlgrey: sim_sram_if.sv doesn't work in Verilator #448

Closed RRozak closed 3 years ago

RRozak commented 3 years ago

It gives errors:

%Error-UNSUPPORTED: ../src/lowrisc_systems_top_earlgrey_verilator_0.1/rtl/top_earlgrey_verilator.sv:280:48: Unsupported: Member call on object 'VARXREF 'tl_h2d'' which is a 'BASICDTYPE 'logic''
%Error: Internal Error: ../src/lowrisc_systems_top_earlgrey_verilator_0.1/rtl/top_earlgrey_verilator.sv:280:6: ../V3Width.cpp:4145: Unlinked pin data type
RRozak commented 3 years ago

I created the test: https://github.com/chipsalliance/UHDM-integration-tests/pull/449

RRozak commented 3 years ago

There are 3 warnings. First can be reproduced by InterfaceField from https://github.com/chipsalliance/UHDM-integration-tests/pull/453

RRozak commented 3 years ago

Removed from the list in https://github.com/antmicro/verilator/pull/479