chipsalliance / UHDM-integration-tests

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Add PatternTypeInNestedModule test #456

Open RRozak opened 3 years ago

RRozak commented 3 years ago

Blocked by https://github.com/chipsalliance/Surelog/issues/1808

RRozak commented 3 years ago

Uhdm verilator prints 28, but the original prints 24

RRozak commented 3 years ago

It looks like that problem is on verilator side. The typespec of parameter is correct, but verilator looks only on the name of the type and assumes that it is the one from current scope.