Closed RRozak closed 3 years ago
I created the test: https://github.com/chipsalliance/UHDM-integration-tests/pull/466
Maybe the problem is with lack of dependency (top_earlgrey.sv), so I will first try to include that module: https://github.com/chipsalliance/UHDM-integration-tests/issues/474
Removed from the list in https://github.com/antmicro/verilator/pull/496
When it is removed from the list, the simulation crashes: