Closed rkapuscik closed 3 years ago
The same errors were thrown by original verilator. In #520 I added missing modules and initialized the parameters. Now there are 2 warnings:
lc_ctrl_pkg.sv:177:60: Operator VAR 'TransTokenIdxMatrix' expects 1323 bits on the Initial value, but Initial value's REPLICATE generates 2987 bits.
prim_generic_otp.sv:367:3: Input port connection 'wmask_i' expects 22 bits on the pin connection, but pin connection's REPLICATE generates 28 bits.
The first is from package that doesn't work (https://github.com/chipsalliance/UHDM-integration-tests/issues/495) and occurs in other modules too. I will wait with it until it is solved. I will start investigating the second now.
The second warning should be fixed by https://github.com/chipsalliance/Surelog/issues/1977
The warning can be reproduced by https://github.com/chipsalliance/UHDM-integration-tests/pull/521
It works after https://github.com/antmicro/verilator/pull/508
After updating Opentitan to newest version, prim_otp.sv is failing with: