I am trying to use uhdm to synthesize a design that contains both verilog files and system verilog files. During synthesis, it reports this error:
/openLANE_flow/designs/opentitan_soc/src/ibex_cs_registers.v:1021: ERROR: Left hand side of 1st expression of procedural for-loop is not a register!
where the corresponding lines in the verilog file are shown below:
1018 always @(*) begin : gen_mhpmcounter_incr
1019 begin : sv2v_autoblock_7
1020 reg [31:0] i;
1021 for (i = 0; i < 32; i = i + 1)
1022 begin : gen_mhpmcounter_incr_inactive
1023 mhpmcounter_incr[i] = 1'b0;
1024 end
1025 end
These verilog files have been synthesized by dc so I am not sure if there is anything that goes wrong with the setting. Any suggestion and help will be appreciated.
I am trying to use uhdm to synthesize a design that contains both verilog files and system verilog files. During synthesis, it reports this error:
where the corresponding lines in the verilog file are shown below:
These verilog files have been synthesized by dc so I am not sure if there is anything that goes wrong with the setting. Any suggestion and help will be appreciated.