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chipsalliance / UHDM-integration-tests

Apache License 2.0
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SERV get miscompiled #598

Closed olofk closed 3 years ago

olofk commented 3 years ago

SERV has a line that looks like this wire co_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];. When opcode is 0x5 the wire should be asserted, but when I compile with Surelog it remains low. If I remove related code that reads the result signal, it behaves as expected again.

Attaching a minimal test case using surelog+uhdm and a reference build using verilator directly + a gtkwave screenshot showing the difference surelog_bug2.tar.gz

surelog_bug

tgorochowik commented 3 years ago

Thanks! We will take a look at this!

rkapuscik commented 3 years ago

Should be fixed by https://github.com/antmicro/verilator/pull/592. I also added your test case in https://github.com/chipsalliance/UHDM-integration-tests/pull/599, but tested this only by verifying that the waveforms are the same between UHDM and original Verilator.

Please check if it's working now for you and report other issues if you encounter any.

olofk commented 3 years ago

Yes! Tested and works fine. Thanks for this. Got it running with a full SERV SoC via FuseSoC+Edalize using the wip surelog branch