chipsalliance / UHDM-integration-tests

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Add Casez test #706

Closed kamilrakoczy closed 1 year ago

kamilrakoczy commented 1 year ago

This PR adds test reported in: https://github.com/antmicro/yosys-systemverilog/issues/1450

Signed-off-by: Kamil Rakoczy krakoczy@antmicro.com

mglb commented 1 year ago

https://github.com/antmicro/yosys-systemverilog/issues/1450 also adds support for casex, can you add a test for it too?

kamilrakoczy commented 1 year ago

Sure, I've also added test case for casex. Note: I needed to adapt plugin a bit to match original yosys frontend: https://github.com/chipsalliance/yosys-f4pga-plugins/pull/451/commits/0af8e42609be2602ab0d8083853b44b7bcd79ced I'm not entirely sure if it is correct, but as original yosys is doing this, I think it is ok to follow this approach.