Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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struct_net::Typespec could be union_typespec #1024
struct_net::Typespec could be union_typespec
Removed assumption that the struct_net::Typespec can only be struct_typespec. C-style cast was hiding the assumption.